The present invention relates to semiconductor packaging technology. The present invention has particular applicability to semiconductor packages containing a substrate comprising fan-out circuitry electrically interconnected by vias.
Ongoing advances in solid-state electronic devices impose continuous demands for integrated circuit devices with increased functionality, density, and performance. In response, multi-chip modules have evolved comprising a printed circuit board substrate to which a series of separate components are directly attached. Multi-chip devices advantageously increase circuit density with attendant improvements in signal propagation speed and overall device weight.
Integrated circuit devices are typically electronically packaged by mounting one or more chips to a substrate, e.g., an alumna circuitized substrate or a copper plated organic substrate, sometime referred to as a chip carrier. Wire bonds are employed to electrically connect input/output (IO) contact pads on each chip to corresponding fan-out circuitry on the circuitized chip carrier substrate. The resulting chip carrier is then typically mounted on a printed circuit board (PCB) and, employing circuitry on the PCB, electrically coupled to other such chip carriers and/or other electronic components mounted on the PCB.
Conventional organic circuitized substrates contain two or more layers of fan-out circuitry on two or more BT layers. Such layers of fan-out circuitry are electrically interconnected by mechanically drilled holes known as vias which are plated and/or filled with electrically conductive material, e.g., copper. Some of the holes extend from the layers of fan-out circuitry to respective lands on the chip carrier substrates, on which are mounted solder balls forming a grid array, thereby generating the expression xe2x80x9cball grid arrayxe2x80x9d. The solder balls are mechanically and electrically connected to corresponding solderable contact pads on the PCB.
Unfortunately, the mechanically drilled holes or vias electrically interconnecting the layers of fan-out circuitry have very large diameters, requiring the spacing between the fan-out wires to be relatively large, thereby limiting the number of chip I/O pads which can be accommodated by the multilayered substrates. Moreover, conventional practices comprise forming the vias in aligned rows. For example, adverting to FIG. 1, an upper surface of chip carrier substrate 10 comprises two rows of substantially aligned vias, one row:of vias substantially aligned with via 11 and another row of vias aligned with via 12. Circuitry lines from such vias illustrated by reference numeral 13 with respect to vias aligned with via 11 and reference number 13A with respect to vias aligned with via 12. The bottom surface of chip carrier substrate 10 is chemically illustrated in FIG. 2 and comprises vias 11 and 12, solder balls 22, and circuitry wiring 23. Such chip carrier substrates have been found to cause failures during various assembling stages, such as die-attaching a semiconductor die or chip to the upper surface of the substrate and molding to encapsulate the semiconductor die on the substrate with a molding compound. In addition, such chip arricer substrates have been found to undergo warpage and bending.
Accordingly, there exists a need for chip carrier substrates exhibiting high strength and rigidity and resistance to warpage and bending for use in semiconductor packaging.
An advantage of the present invention is a chip carrier substrate exhibiting high strength and rigidity and improved resistance to warpage and bending.
Additional advantages and features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a substrate for attaching a semiconductor die to a printed circuit board, the substrate comprising: an upper surface containing electrically functional metal lines; and a lower surface containing electrically functional metal lines; wherein, at least one of the upper and lower surfaces contains an electrically non-functional metal area for improved strength and rigidity and reduced warpage and bending.
Embodiments of the present invention comprise substrates wherein each of the upper surface and lower surface contains at least one electrically non-functional area of copper (Cu) or a Cu alloy, as in the form of a grid. Embodiments of the present invention further include substrates wherein the ratio of the total area of electrically functional lines and electrically non-functional Cu or Cu alloy areas on one of the upper surface and lower surface is about 55% to about 100%, such as about 60% to about 80%, of the total area of the electrically functional lines and electrically non-functional Cu or Cu alloy areas on the other of the lower surface and the upper surface of the substrate. Embodiments of the present invention further comprise substrates having vias extending through the substrate between the upper and lower surfaces interconnecting the electrically functional Cu or Cu alloy lines on the upper and lower surfaces, wherein the vias are offset from one another such that less than 20% of the vias are aligned. Embodiments of the present invention further comprise substrates having at least 48 vias interconnecting fan-out circuitry, and further include a circuit assembly comprising at least one semiconductor die attached to a printed circuit board by means of a substrate in accordance with the present invention.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawing and description is to be regarded as illustrative in nature, and not as restrictive.